module vgalab2(
CLOCK_50,
CLOCK_27,
KEY,
SW,
LEDR,
LEDG,
TD_RESET,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK,
VGA_SYNC,
VGA_R,
VGA_G,
VGA_B,
dieKey,
rst,
rst2
);


//	Clock Input
  input CLOCK_50;	//	50 MHz
  input CLOCK_27;     //      27 MHz
  input rst;
  input rst2;
  input dieKey;
//	Push Button
  input [3:1] KEY;      //	Pushbutton[3:0]
//	DPDT Switch
  input [16:0] SW;		//	Toggle Switch[17:0]

//	LED
  output [8:0]	LEDG;  //	LED Green[8:0]
  output [17:0] LEDR;  //	LED Red[17:0]
//	TV Decoder
//TD_DATA,    	//	TV Decoder Data bus 8 bits
//TD_HS,		//	TV Decoder H_SYNC
//TD_VS,		//	TV Decoder V_SYNC
  output TD_RESET;	//	TV Decoder Reset
// VGA
  output VGA_CLK;   						//	VGA Clock
  output VGA_HS;							//	VGA H_SYNC
  output VGA_VS;							//	VGA V_SYNC
  output VGA_BLANK;						//	VGA BLANK
  output VGA_SYNC;						//	VGA SYNC
  output [9:0] VGA_R;   						//	VGA Red[9:0]
  output [9:0] VGA_G;	 						//	VGA Green[9:0]
  output [9:0] VGA_B; 

wire RST;
assign RST = KEY[1];

// reset delay gives some time for peripherals to initialize
wire DLY_RST;
Reset_Delay r0(	.iCLK(CLOCK_50),.oRESET(DLY_RST) );

// Send switches to red leds 
assign LEDR = SW;

// Turn off green leds
assign LEDG = 8'h00;

wire [6:0] blank = 7'b111_1111;

// blank unused 7-segment digits
assign HEX0 = blank;
assign HEX1 = blank;
assign HEX2 = blank;
assign HEX3 = blank;
assign HEX4 = blank;
assign HEX5 = blank;
assign HEX6 = blank;
assign HEX7 = blank;

wire		VGA_CTRL_CLK;
wire		AUD_CTRL_CLK;
wire [9:0]	mVGA_R;
wire [9:0]	mVGA_G;
wire [9:0]	mVGA_B;
wire [9:0]	mCoord_X;
wire [9:0]	mCoord_Y;

assign	TD_RESET = 1'b1; // Enable 27 MHz

VGA_Audio_PLL 	p1 (	
	.areset(~DLY_RST),
	.inclk0(CLOCK_27),
	.c0(VGA_CTRL_CLK),
	.c1(AUD_CTRL_CLK),
	.c2(VGA_CLK)
);


textbox u3(
	.iCLK1(VGA_CLK),
	.iCLK2(VGA_CTRL_CLK),
	.dieKey(dieKey),
	.guess(SW[0]),
	.rstKey(rst),
	.CLOCK_50(CLOCK_50),
	.px(mCoord_X),
	.py(mCoord_Y),
	.guessed(keydata),
	.valid(valid),
	.valid2(valid2),
	.valid3(valid3),
	.pixel(pixel),
	.pixel2(pixel2),
	.pixel3(pixel3),
	.rst2(rst2)
);
wire valid, pixel;//shapes
wire valid2, pixel2; //letters
wire valid3, pixel3; //cutouts 



wire s = valid & pixel;
wire s2 = valid2 & valid3 & pixel2;
wire s3 = s | s2;
wire s4 = valid3 & pixel3;
parameter WHITE = 10'h3FF;
parameter BLACK = 10'h000;

assign mVGA_R = (s3? WHITE: 0);
assign mVGA_G = (s3? WHITE: 0);
assign mVGA_B = (s3? WHITE: 300);


vga_sync u1(
   .iCLK(VGA_CTRL_CLK),
   .iRST_N(DLY_RST&KEY[1]),	
   .iRed(mVGA_R),
   .iGreen(mVGA_G),
   .iBlue(mVGA_B),
   // pixel coordinates
   .px(mCoord_X),
   .py(mCoord_Y),
   // VGA Side
   .VGA_R(VGA_R),
   .VGA_G(VGA_G),
   .VGA_B(VGA_B),
   .VGA_H_SYNC(VGA_HS),
   .VGA_V_SYNC(VGA_VS),
   .VGA_SYNC(VGA_SYNC),
   .VGA_BLANK(VGA_BLANK)
);


endmodule